The present invention relates to a method by which the conditions are established for the etching step in a manufacturing process of semiconductor devices or thin film magnetic heads, for instance, in particular the step of forming holes for inter-layer connection or the etching step of forming holes known as contact holes, via holes or through holes can ensure stable conduction and a method of performing periodic condition checkups (quality control: QC), a device therefor and a machining method for semiconductor devices using this condition setting method.
In recent years, as holes for inter-layer connection are increasingly reduced in diameter and raised in aspect ratio along with the use of ever finer patterns, the need is rising for measuring techniques which can ensure accurate establishment of conditions for the hole etching step and performance of periodic condition checkups (quality control: QC) in a reduced number of man-hours. Whereas dry etching typically including plasma etching and wet etching using an etching solution are generally known, dry etching is mainly used for fine machining.
According to the prior art, regarding establishment of the conditions of the etching step and performance of periodic condition checkups (quality control: QC), in particular the step of forming holes for inter-layer connection or the etching step of forming holes known as contact holes, via holes or through holes, there is no method of direct nondestructive measurement, and measurement is carried out by one or another of the following methods.
One method is to perform confirmation of conduction electrically by using a dedicated test element group (TEG) wafer in which a probing pad is formed by arranging holes for inter-layer connection in a chain form. This method requires measurement of resistances after the formation of under layer wiring, holes for inter-layer connection and upper layer wiring, and accordingly the TEG wafer for use in the measurement has to go though many steps for checking up the conditions of etching to form holes for inter-layer connection, resulting in an extra cost and length of time. If any problem is found, a section of the holes for inter-layer connection should be cut out with a focused ion beam (FIB) or the like to be observed and analyzed through a scanning electron microscope (SEM) or otherwise, which also is time consuming and costly.
For the routine monitoring of deviations from etcher conditions (quality control: QC), either the TEG cited above is used, or a line-and-space test pattern is formed by etching, and the level gaps in this pattern are measured with a stylus profiler or an atomic force microscope (AFM). Another known method is optical CD (OCD) by which the scattering of light by a line-and-space test pattern is measured and the three-dimensional shape parameters are estimated. However, since the test pattern is not a hole pattern, the etching pattern is offset, and this offset has to be compensated for, making it impossible to directly confirm the etching conditions of holes.
Also, regarding the conditions of etching to form holes, it is essential to make sure that the holes formed in the insulator layer reach the wiring pattern layer of the under layer. For instance, the Japanese Patent Application Laid-Open No. 2000-9437 discloses a method to optically measure the thickness of an insulator layer formed over a wiring pattern or the like, but this disclosure proposes nothing regarding a method to check and measure whether or not the holes have reached the under layer.
By still another method, the conduction or non-conduction of holes for inter-layer connection is detected according to differences in voltage contrast when the etched object is irradiated with an electron beam. Although this method permits detection of high resistances, there is no way to assess how much extra etching is done over the minimum required etching depth (a state of over-etching) at the time of conduction. What is essentially desired to be known is, when holes for inter-layer connection 102 are bored into an under layer wiring layer 101 in the insulator layer 100, whether the holes penetrate the wiring layer 101 neither too much nor too little to achieve an appropriate over-etched state 102a, they do not reach the wiring layer 101 in a non-conducting state 102b or there is a state of excessive over-etch 102c as shown in the sectional view of FIG. 2. Even if only the whole depth d is measured with a stylus profiler, it is impossible to know how the under layer 101 is etched or not etched because the depth of the insulator layer 100 varies.
Whereas a semiconductor device uses many hole patterns, known as via holes, contact holes or through holes, to establish electrical connection between a conducting under layer and a wiring layer above with an insulator layer in-between, the establishment of the conditions for etching to bore these holes can be achieved only by determination of a good or faulty state according to voltage contrast under irradiation with an electron beam or a destructive test with a sectional SEM, but there is no nondestructive way of quantitative evaluation of the state of etching.